4 research outputs found
Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches
In this work, we study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a fourterminal switch controlled by a Boolean literal. These types of arrays are commonly called as switching lattices. We propose
optimal and heuristic algorithms that minimize lattice sizes to implement a given Boolean function. The algorithms are mainly
constructed on a technique that finds Boolean functions of lattices having independent inputs. This technique works recursively
by using transition matrices representing columns and rows of the lattice. It performs symbolic manipulation of Boolean literals
as opposed to using truth tables that allows us to successfully find Boolean functions having up to 81 variables corresponding to a
9×9-lattice. With a Boolean function of a certain sized lattice, we check if a given function can be implemented with this lattice
size by defining the problem as a satisfiability problem. This process is repeated until a desired solution is found. Additionally, we
fix the previously proposed algorithm that is claimed to be optimal. The fixed version guarantees optimal sizes. Finally, we perform
synthesis trials on standard benchmark circuits to evaluate the proposed algorithms by considering lattice sizes and runtimes in
comparison with the recently proposed three algorithms.This work is supported by the EU-H2020-RISE project NANOxCOMP
#691178 and the TUBITAK-Career project #113E760
Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
Our European Union’s Horizon-2020 project aims
to develop a complete synthesis and performance optimization
methodology for switching nano-crossbar arrays that leads to
the design and construction of an emerging nanocomputer.
Within the project, we investigate different computing models
based on either two-terminal switches, realized with field effect
transistors, resistive and diode devices, or four-terminal switches.
Although a four-terminal switch based model offers a significant
area advantage, its realization at the technology level needs
further justifications and raises a number of questions about its
feasibility. In this study, we answer these questions. First, by using
three dimensional technology computer-aided design (TCAD)
simulations, we show that four-terminal switches can be directly
implemented with the CMOS technology. For this purpose, we
try different semiconductor gate materials in different formations
of geometric shapes. Then, by fitting the TCAD simulation data
to the standard CMOS current-voltage equations, we develop a
Spice model of a four-terminal switch. Finally, we successfully
perform Spice circuit simulations on four-terminal switches with
different sizes. As a follow-up work within the project, we will
proceed to the fabrication step.This work is part of a project that has received funding from the
European Union’s H2020 research and innovation programme under the
Marie Skłodowska-Curie grant agreement No 691178, and supported by the
TUBITAK-Career project #113E760
Integrated Synthesis Methodology for Crossbar Arrays
Nano-crossbar arrays have emerged as area and power efficient
structures with an aim of achieving high performance computing
beyond the limits of current CMOS. Due to the stochastic nature
of nano-fabrication, nano arrays show different properties both
in structural and physical device levels compared to conventional
technologies. Mentioned factors introduce random characteristics
that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic
technology preference for switching elements, defect or fault rates
of the given nano switching array and the variation values as well
as their effects on performance metrics including power, delay, and
area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization
algorithms for each step of the process.This work is part of a project that has received funding from the
European Union’s H2020 research and innovation programme under the
Marie Skłodowska-Curie grant agreement No 691178, and supported by the
TUBITAK-Career project #113E76